The Design of A 10-Bit CMOS Pipelined Analog-to-Digital Converter

• Main Authors: Kuo, Kuo-Jen, 郭國仁
• Other Authors: Liou Wan-Rone
• Format: Others
• Language: zh-TW
• Published: 1997
• Online Access: http://ndltd.ncl.edu.tw/handle/51300230003792429799

碩士 === 國立海洋大學 === 電機工程學系 === 85 === Besides the high-speed and the high-resolution characteristics, the 10-b nine-stage pipelined analog-to-digital converter(ADC) can satisfy the low-power dissipation requirement of portable video devices and communication systems. The ADC architecture includes eight 1.5-bit stages and one 2-bitstage. Each 1.5-bit stage contains two comparators and a switched- capacitorcircuit which is composed of an operational amplifier, capacitors and NMOSswitches, and resistor string. The 2-bit stage which contains three comparators is a flash ADC structure. The comparator is composed of a folded-cascode amplifier circuit and a current-triggered latch. The purpose of switched-capacitor circuit is to achievethe multiple functions of digital-to-analog converter(DAC), subtraction, and amplification. Without usingabsolutely accurate capacitance, switched-capacitor require only relativeaccurate capacitance. It is therefore much easier to befabricated for today'sprocessing technology. This thesis implements the design of a 10-b 2M sample/s nine-stage pipelinedADC.The input signal range of ADC is from 0.2V to 1.6V. It is fabricated with0.5um double-poly-double-metal CMOS technology. Power supply of 3.3V is usedin this ADC chip design in order to achieve the low-voltage and low-power specifications. The simulation results show that the power dissipation of ADCis 28mW and that the integral nonlinearity is +-1LSB. Includingg boththe analog and digital parts, layout area of the core circuit is 2.55mm x0.95mm.