| Summary: | 碩士 === 國立臺灣大學 === 電機工程學系 === 85 === Recently, phase-locked loop (PLL) has been widely used in the
fields ofcomputers and communications. A PLL-based circuit can
synchronize an outputsignal whose frequency is adjustable to
satisfy the specification requirementswith a reference clock in
frequency as well as in phase. In the traditional PLL, a low-
pass filter (LPF) consisting of resistors andcapacitors is
utilized to get rid of the high frequency signal generated by
itscharge-pump circuit. However, resistors and capacitors in the
integrated circuits have great variation in their physical
values. Hence, an all-digital phase-locked loop (ADPLL) scheme
is proposed and designed to conquer the mentioned drawbacks of
the traditional PLL. The charge-pump circuit as well as LPF is
not necessary in the ADPLL. Moreover, the digital nature of the
ADPLL makes it possible to achieve very fast lock time
ascompared to the traditional PLL. This paper reports the
design of an ADPLL-based programmable clock generatorthat has
been implemented with integrated circuits. This ADPLL circuit
has a wide output frequency range over 8MHz to 150MHz.
Experimental results showthat its output signal jitter is less
than 150ps at 80MHz, with lock time lessthan 1us at its
reference clock of 30MHz.
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