| Summary: | 碩士 === 國立台灣工業技術學院 === 電子工程技術研究所 === 85 === In modern digital communication systems, error-correction
codes have been widely used to reduce the bit error rate of
transmitted data. Among the various error-correction codes, the
convolutional code is the most widely used one. For decoding the
convolutional code, Viterbi algorithm is the most popular one
that can be used for this purpose. This algorithm is a maximum
likelihood decoder (MLD) that receives information, computes any
possible path on the trellis diagram, and then finds an optimal
path with the best path metric. In the thesis, by using
Viterbi algorithm, we propose a node-parallel architecture for
Viterbi decoder, which can process two kinds of (3,1,2) binary
convolutional code generated by different generator matrices and
realize Viterbi decoder chip based on the cell library approach,
which targets to COMPASS 0.6um standard cell library and the
TSMC 0.6 um CMOS SPDM technology. The die size of Viterbi
decoder is 2264 x 2067 umand dissipates 118.173 mW at the
operating frequency of 50 MHz under worst-case conditions
(VDD=4.75V and TA=70℃). With this clock rate, the chip can
achieve a decoding rate of 50 Mb/s.
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