| Summary: | 碩士 === 大同工學院 === 資訊工程學系 === 85 === Reed-Solomon 碼可以說是世界上最常使用於數位錯誤控制的一種碼。
在這篇論文中，設計了一個修正3階段管線式且具有可拭性符號及錯誤更
正能力之Reed-Solomon碼解碼器。在第一個階段是負責錯誤徵兆以及可拭
性符號位置方程式之計算。在第二個階段是使用Berlekamp-Massey的演算
法去計算修正過的錯誤徵兆及錯誤位置方程式，而這個階段的另一部份是
做錯誤及可拭性符號位置方程式還有錯誤和可拭性符號大小程度方程式的
計算。第三個階段，是利用Chien搜尋和Forney演算法去找出可拭性符號
和錯誤的位置與大小，將其更正後，輸出正確的代碼。設計出來晶片之佈
局大約為7741.75*8684.86熤。第一筆資料大約在695時脈可算出結果，
之後會在每255時脈循環中輸出結果。
The Reed-Solomon codes can be claimed safely that they are the
most frequentlyused digital error control codes in the world. In
this thesis, we design amoeified 3 pipeline stages Reed-Solomon
code decoder with error and erasurecorrecting. The stage I deals
with the syndrome and erasure locator polynomialcalculation. The
stage II deals with generating the modified syndrome and
errorlocator polynomial calculation by using the Berlekamp-
Massey's algorithm. Thesecond part of this stage, it produces
error/erasure magnitudes polynomial anderror/erasure locators
polynomial. The stage III deals with correcting the error and
erasure then outputs the correct codeword. The error/erasure
locators andthe error/erasure magnitudes are calculated
simultaneous by using Chien searchprocedure and modified Forney'
s algorithm, which proposed in this thesisrespectively. The chip
is generating by Compass 0.6 library and the area of thechip is
about 7.741*8.684mm? The first data will be generated in 695
clockcycles and the data will output in 255 clock cycles.
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