The Implementation and Analysis of the CELP Coder with a Dsp Processor

碩士 === 大同大學 === 電機工程研究所 === 85 === Nowadays, in the popular internet and personal communication network, the applications of digital speech signal will be promising and will be applied widely, so there is no doubt that the coder with low bit rates and high synthetic speech quality is important...

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Main Authors: Chiu, Ming-Fung, 邱明鋒
Other Authors: Chou, Chun-Hsien
Format: Others
Language:zh-TW
Published: 1997
Online Access:http://ndltd.ncl.edu.tw/handle/84560912385965372785
id ndltd-TW-085TTU03442001
record_format oai_dc
spelling ndltd-TW-085TTU034420012016-07-01T04:16:04Z http://ndltd.ncl.edu.tw/handle/84560912385965372785 The Implementation and Analysis of the CELP Coder with a Dsp Processor 以數位訊號處理器實現與分析CELP語音編碼器 Chiu, Ming-Fung 邱明鋒 碩士 大同大學 電機工程研究所 85 Nowadays, in the popular internet and personal communication network, the applications of digital speech signal will be promising and will be applied widely, so there is no doubt that the coder with low bit rates and high synthetic speech quality is important in this field. Code Excited Linear Prediction (CELP) is developed base on linear prediction and code excitation model, the scheme with potential to synthesize high speech quality at low bit rates. For example, the Federal Standard 1016 speech CODEC (encoder, decoder) can achieve high synthetic speech quality under 4.8k bps. Federal Standard 1016 speech encoder has three basic features: (1) Short-term linear prediction analysis, (2) Long-term adaptive codebook search and (3) Innovation stochastic codebook search. The objective of linear prediction analysis is to model physical shape of human vocal tract. Adaptive codebook is used to emulate the vibration of human vocal cords in order to produce period phenomenon of speech waveform. Stochastic codebook represents the air flow from lungs to lips. In this thesis, we will implement the Federal Standard 1016 speech CODEC with C language and discuss the problems we met in detail. Meanwhile, we will use TMS320C30 development system to implement the Federal Standard 1016 speech CODEC and analyze the implementation process. Chou, Chun-Hsien 周俊賢 1997 學位論文 ; thesis 56 zh-TW
collection NDLTD
language zh-TW
format Others
sources NDLTD
description 碩士 === 大同大學 === 電機工程研究所 === 85 === Nowadays, in the popular internet and personal communication network, the applications of digital speech signal will be promising and will be applied widely, so there is no doubt that the coder with low bit rates and high synthetic speech quality is important in this field. Code Excited Linear Prediction (CELP) is developed base on linear prediction and code excitation model, the scheme with potential to synthesize high speech quality at low bit rates. For example, the Federal Standard 1016 speech CODEC (encoder, decoder) can achieve high synthetic speech quality under 4.8k bps. Federal Standard 1016 speech encoder has three basic features: (1) Short-term linear prediction analysis, (2) Long-term adaptive codebook search and (3) Innovation stochastic codebook search. The objective of linear prediction analysis is to model physical shape of human vocal tract. Adaptive codebook is used to emulate the vibration of human vocal cords in order to produce period phenomenon of speech waveform. Stochastic codebook represents the air flow from lungs to lips. In this thesis, we will implement the Federal Standard 1016 speech CODEC with C language and discuss the problems we met in detail. Meanwhile, we will use TMS320C30 development system to implement the Federal Standard 1016 speech CODEC and analyze the implementation process.
author2 Chou, Chun-Hsien
author_facet Chou, Chun-Hsien
Chiu, Ming-Fung
邱明鋒
author Chiu, Ming-Fung
邱明鋒
spellingShingle Chiu, Ming-Fung
邱明鋒
The Implementation and Analysis of the CELP Coder with a Dsp Processor
author_sort Chiu, Ming-Fung
title The Implementation and Analysis of the CELP Coder with a Dsp Processor
title_short The Implementation and Analysis of the CELP Coder with a Dsp Processor
title_full The Implementation and Analysis of the CELP Coder with a Dsp Processor
title_fullStr The Implementation and Analysis of the CELP Coder with a Dsp Processor
title_full_unstemmed The Implementation and Analysis of the CELP Coder with a Dsp Processor
title_sort implementation and analysis of the celp coder with a dsp processor
publishDate 1997
url http://ndltd.ncl.edu.tw/handle/84560912385965372785
work_keys_str_mv AT chiumingfung theimplementationandanalysisofthecelpcoderwithadspprocessor
AT qiūmíngfēng theimplementationandanalysisofthecelpcoderwithadspprocessor
AT chiumingfung yǐshùwèixùnhàochùlǐqìshíxiànyǔfēnxīcelpyǔyīnbiānmǎqì
AT qiūmíngfēng yǐshùwèixùnhàochùlǐqìshíxiànyǔfēnxīcelpyǔyīnbiānmǎqì
AT chiumingfung implementationandanalysisofthecelpcoderwithadspprocessor
AT qiūmíngfēng implementationandanalysisofthecelpcoderwithadspprocessor
_version_ 1718330734894120960