Performance Evaluation of Decoder Architecture for Converting X86 Instructions into Micro-operations
碩士 === 元智大學 === 電機與資訊工程研究所 === 85
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| Online Access: | http://ndltd.ncl.edu.tw/handle/73208119817948097507 |
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ndltd-TW-085YZU054460122016-08-22T04:16:53Z http://ndltd.ncl.edu.tw/handle/73208119817948097507 Performance Evaluation of Decoder Architecture for Converting X86 Instructions into Micro-operations 評估解碼器轉換X86指令至其微指令之效能 蔡志明 碩士 元智大學 電機與資訊工程研究所 85 學位論文 ; thesis 77 zh-TW |
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NDLTD |
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zh-TW |
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Others
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NDLTD |
| description |
碩士 === 元智大學 === 電機與資訊工程研究所 === 85 |
| author |
蔡志明 |
| spellingShingle |
蔡志明 Performance Evaluation of Decoder Architecture for Converting X86 Instructions into Micro-operations |
| author_facet |
蔡志明 |
| author_sort |
蔡志明 |
| title |
Performance Evaluation of Decoder Architecture for Converting X86 Instructions into Micro-operations |
| title_short |
Performance Evaluation of Decoder Architecture for Converting X86 Instructions into Micro-operations |
| title_full |
Performance Evaluation of Decoder Architecture for Converting X86 Instructions into Micro-operations |
| title_fullStr |
Performance Evaluation of Decoder Architecture for Converting X86 Instructions into Micro-operations |
| title_full_unstemmed |
Performance Evaluation of Decoder Architecture for Converting X86 Instructions into Micro-operations |
| title_sort |
performance evaluation of decoder architecture for converting x86 instructions into micro-operations |
| url |
http://ndltd.ncl.edu.tw/handle/73208119817948097507 |
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