Design of a Low-Power VLSI Cell Library Exploiting Different Types of CMOS Logic Circuits

Design of a Low-Power VLSI Cell Library Exploiting Different Types of CMOS Logic Circuits

碩士 === 國立中正大學 === 電機工程學系 === 86 === A cell library which can be used to design a low-power VLSI is proposed. lsoThe usage of this cell library is compatible with the existent EDA mm CMOSenvironment.m the post-layout simulation, the power reduction ration...

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Bibliographic Details
Main Authors:	Huang, Po-Shin, 黃柏勳
Other Authors:	Jinn-Shyan Wang
Format:	Others
Language:	zh-TW
Published:	1998
Online Access:	http://ndltd.ncl.edu.tw/handle/61109740573820096504

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