| Summary: | 碩士 === 中原大學 === 資訊工程研究所 === 86 === In this thesis, we describe the design and implementation of an ALU (Arithmetic and Logic Unit) for Java Chip. ALU of Java chip can execute the functions of plus,minus, multiply, divide, one''s complement, two''s complement, shift, data type transfer, logic operation, and flags set operations. In this thesis, ALU of Java chip include adder / subtracter, shifter, logic unit, multiplier, divider and decoder. Beside the design and implementation of the ALU functions, design verification are also iscussed in this thesis. All of these logic circuits are described in Verilog program, compiled by synthesis tool of Synopsys and get a complete circuit description. The design of ALU is verified by the Verilog simulation program, it can prove the correction of the design and implementation.
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