| Summary: | 碩士 === 國立交通大學 === 資訊工程學系 === 86 === Instruction fetch is the first pipeline stage in microprocessors
and itinfluences the performance of microprocessors
significantly. In a superscalarmicroprocessor, the instruction
fetcher must provide multiple instructions tothe decoders each
clock cycle. However, in x86 architecture, the variable-length
instruction set and the complex addressing system makes fetching
multiple instructions in a clock cycle difficult. In this thesis
we designed a high-bandwidth instruction fetcher for x86
superscalar environment. Predecode information is used to help
identifying multiple instructions in one clockcycle and
assigning duplicated instructions to the decoders for decoding.
Amechanism called the Address Queue is proposed for maintaining
instruction addresses. It simplifies the data routing in x86
microprocessors. Simulationresults showed that because the fetch
rule of our design is deduced from the behavior of benchmark
programs, our design can provide instruction decoders with
sufficient instruction steadily. Synthesis results showed that
our design can reach the same clock rate of currently available
x86 superscalar microprocessors if the same process technology
is used.
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