Design of an Instruction Fetcher with Address Queue for x86 Superscalar Microprocessors
碩士 === 國立交通大學 === 資訊工程學系 === 86 === Instruction fetch is the first pipeline stage in microprocessors and itinfluences the performance of microprocessors significantly. In a superscalarmicroprocessor, the instruction fetcher must provide mul...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | zh-TW |
| Published: |
1998
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| Online Access: | http://ndltd.ncl.edu.tw/handle/34393590378199630270 |