Timing Recovery for 100Base-T4
碩士 === 國立中央大學 === 電機工程學系 === 86 === The demands of data communications rise rapidly. The 100Base- T4 is the next generation of 10Base system, which is the most popular local area network system today. The 100Base-T4 has almost te...
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| Format: | Others |
| Language: | zh-TW |
| Published: |
1998
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| Online Access: | http://ndltd.ncl.edu.tw/handle/73641987805676183777 |
| Summary: | 碩士 === 國立中央大學 === 電機工程學系 === 86 === The demands of data communications rise rapidly. The 100Base-
T4 is the next generation of 10Base system, which is the most
popular local area network system today. The 100Base-T4
has almost ten times capacity than 10Base system and still
uses CSMA/CD MAC protocol. This thesis focuses on the
timing recovery subsystem in 100Base-T4 standard and propose
an architecture for it. This architecture includesa pulse
shaping filter on the transmitter and an adaptive filter and
the timing recovery on the receiver. A phase detector in the
timing recovery loop is proposed for extracting timing
information in this three level PAM baseband system. The
adaptive filter is also proposed with a control method based on
MMSE algorithm. The circuit level
designs and simulations use TSMC 0.6um SPTM CMOS technology.
The simulation results show that the power consumption of the
receiver part is about 180mW with 3V power supply.
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