Design and Research of High Voltage P-channel Lateral DMOSFET in CMOS Technology

• Main Authors: Chang, Hsiuang-Chung, 張湘忠
• Other Authors: Hsu, Ching-Hsiang
• Format: Others
• Language: zh-TW
• Published: 1998
• Online Access: http://ndltd.ncl.edu.tw/handle/32403611941623064445

碩士 === 國立清華大學 === 電機工程研究所 === 86 === 　　The high-voltage lind driving function in most telecommunication systems and planar display circuits is performed by dedicated HVICs or external discrete high voltage components. However, high-voltage line drivers, when integrated with low-voltage signal processing circuits on a single chip, can eliminate most of the external circuitry and reduce power consumption while increasing reliability. Such advantages become more appealing when an advanced technology is empowered with high voltage capability providing both complex DSP and line driving function on single chip. 　　To promote the performance of systems, Rsp and BV of high voltage devices are the major concerns in HVIC. The purpose of this work was to develop high performance 60V rated HVMOSFET employing RESURF principle and using as much of the existing conventional 1.0um CMOS process steps as possible. 　　Here emphasis is on a methodology of developing a high performance HVMOSFET in a low-voltage logic circuit process. An up front modeling study using Medici and Tsuprem4 was completed to look at device performance vs. fabrication variables. The simulation results help the formation of the window of process parameters and the various geometry ranges of devices. The relationship of trade-off between BV and Rsp are certified by measured data from hardware. Response Surface Analysis was applied to help us to get a more sensitive view in relationship between performance of devices and process parameters and cell geometry