Low-Power CMOS Static Random Access Memory Design

碩士 === 國立臺灣大學 === 電機工程學系 === 86 === Low-power dissipation is the trend on the development of static random access memory(SRAM). In order to reduce the power dissipation, the power supply vlotage reduction is necessary. This thesis will describe the...

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Bibliographic Details
Main Authors:	Huang, Chit-Keng, 黃啟耕
Other Authors:	James B. Kuo
Format:	Others
Language:	zh-TW
Published:	1998
Online Access:	http://ndltd.ncl.edu.tw/handle/01014465211886842238

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record_format	oai_dc
spelling	ndltd-TW-086NTU004420682016-06-29T04:13:46Z http://ndltd.ncl.edu.tw/handle/01014465211886842238 Low-Power CMOS Static Random Access Memory Design 低功率互補式金氧半靜態隨機存取記憶體之設計 Huang, Chit-Keng 黃啟耕碩士國立臺灣大學電機工程學系 86 Low-power dissipation is the trend on the development of static random access memory(SRAM). In order to reduce the power dissipation, the power supply vlotage reduction is necessary. This thesis will describe the problems and the suitable circuit techniques under the low-voltage operation. In addition, this thesis reports a technique by using the pre-output buffer and bootstrapped driver circuit, which can increase the data output speed for SRAM. Based on the simulation result, using the pre-output buffer and bootstrapped driver circuit, there has evident improvement of the data output delay when the supply voltage has been scaled down. Under the 40MHz operating frequency and 1.5V power supply, the data output delay has been reduced 7.6ns. The power dissipation and address access time are 10mW and 23.7ns, respectively. James B. Kuo 郭正邦 --- 1998 學位論文 ; thesis 76 zh-TW
collection	NDLTD
language	zh-TW
format	Others
sources	NDLTD
description	碩士 === 國立臺灣大學 === 電機工程學系 === 86 === Low-power dissipation is the trend on the development of static random access memory(SRAM). In order to reduce the power dissipation, the power supply vlotage reduction is necessary. This thesis will describe the problems and the suitable circuit techniques under the low-voltage operation. In addition, this thesis reports a technique by using the pre-output buffer and bootstrapped driver circuit, which can increase the data output speed for SRAM. Based on the simulation result, using the pre-output buffer and bootstrapped driver circuit, there has evident improvement of the data output delay when the supply voltage has been scaled down. Under the 40MHz operating frequency and 1.5V power supply, the data output delay has been reduced 7.6ns. The power dissipation and address access time are 10mW and 23.7ns, respectively.
author2	James B. Kuo
author_facet	James B. Kuo Huang, Chit-Keng 黃啟耕
author	Huang, Chit-Keng 黃啟耕
spellingShingle	Huang, Chit-Keng 黃啟耕 Low-Power CMOS Static Random Access Memory Design
author_sort	Huang, Chit-Keng
title	Low-Power CMOS Static Random Access Memory Design
title_short	Low-Power CMOS Static Random Access Memory Design
title_full	Low-Power CMOS Static Random Access Memory Design
title_fullStr	Low-Power CMOS Static Random Access Memory Design
title_full_unstemmed	Low-Power CMOS Static Random Access Memory Design
title_sort	low-power cmos static random access memory design
publishDate	1998
url	http://ndltd.ncl.edu.tw/handle/01014465211886842238
work_keys_str_mv	AT huangchitkeng lowpowercmosstaticrandomaccessmemorydesign AT huángqǐgēng lowpowercmosstaticrandomaccessmemorydesign AT huangchitkeng dīgōnglǜhùbǔshìjīnyǎngbànjìngtàisuíjīcúnqǔjìyìtǐzhīshèjì AT huángqǐgēng dīgōnglǜhùbǔshìjīnyǎngbànjìngtàisuíjīcúnqǔjìyìtǐzhīshèjì
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Low-Power CMOS Static Random Access Memory Design

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