Design and Implementation of a Low-Voltage Reconfigurable Adaptive Filter

• Main Authors: Yang, Chih-chieh, 楊智傑
• Other Authors: Chiueh Tzi-Dar
• Format: Others
• Language: en_US
• Published: 1998
• Online Access: http://ndltd.ncl.edu.tw/handle/15392650632224552406

碩士 === 國立臺灣大學 === 電機工程學系 === 86 === A reconfigurable linear adaptive filter chip is proposed, implemented and tested in this thesis. The filter chip has a feedforward module and a feedback module. The feedforward module contains eight half complex taps and is capable of comprising a feedforward equalizer (FFE), fractionally-spaced equalizer (FSE), spatial diversity equalizer, adaptive beamformer or interference canceler. The feedback module has eight full complex taps and can cooperate with the feedforward module to form a decision-feedback equalizer (DFE). It can be programmed to accept several modulation formats, including quaternary phase-shift keying (QPSK), 16, and 64 quadrature amplitude modulation (QAM). Both the feedforward and feedback module also incorporate coefficient updating circuitry for implementing the sign-LMS adaptive algorithm with user-selectable adaptation stepsize. Several chips can be cascaded to form longer tap length and/or higher diversity level. To increase chip throughput and decrease power consumption, the multiple supply-voltage strategy is applied. A novel built-in charge pump is included to provide a higher voltage for circuits on the critical path of the feedback module, while other parts of the feedback module are well pipelined and supplied with a lower voltage. The transistor count of the chip is 247,556 within 6,332x6,332 mu^2 die area manufactured in 0.6 mu single poly triple metal CMOS technology. The core power consumption of the feedforward module is 32mW at 15MHz, 3.0V, and that of the feedback module is 23mW at 18.5MHz, 3.0V, 1.5V supply voltage.