The Design and Implementation of an 8-bit CMOS Video Digital-to-Analog Converter

• Main Authors: Tsay Jenn Shan, 蔡振杉
• Other Authors: Lin Ming-Bo
• Format: Others
• Language: zh-TW
• Published: 1998
• Online Access: http://ndltd.ncl.edu.tw/handle/59647897166753324972

碩士 === 國立臺灣科技大學 === 電子工程技術研究所 === 86 === The DAC is widely used in many applications, such as audio, video, communication, DSP system, etc. In this thesis, we design a current output mode DAC for video applications. In order to achieve high differential linearity and guarantee mon-otonicity, a structure that combines a non-weighted current cell ma-trix and two weighted current cells is used. This structure is furt-her pipelined to reduce the conversion time and the output glitch energy. In this thesis, two DAC chips have been designed. The experimentalresults of the first DAC chip show that DNL, INL, glitch energy, and average power dissipation at the maximum conversion rate of 33.3MHz are 0.6LSB, -2.25LSB, 0.6uVS , and 60mW, respectively. According to the design experiences and the experimental results from the first DAC chip, an improved one is designed and fabricated by using 0.6 single poly triple metal (SPTM) CMOS process.It occup-ies 760×1000 um^2 area, excluding I/O pad, and operates at 3.3V. The input of it is an 8-bit binary code with TTL compatible and full-scale output current is 13.3mA. The results of post-layout simulation show that DNL, INL, glitch energy, and average power dissipation at the maximum conversion rate of 58.8MHz are 0.07LSB, -0.3LSB, 5pVS, and 50mW, respectively.