Design of a BP-based Neural Net Processor for Computing the BPN Algorithm-

• Main Authors: Lue Wang-Chi, 劉萬吉
• Other Authors: Chen-mie Wu-
• Format: Others
• Language: zh-TW
• Published: 1998
• Online Access: http://ndltd.ncl.edu.tw/handle/62761234380647516386

碩士 === 國立臺灣科技大學 === 電子工程技術研究所 === 86 === This thesis is related to the design and implementation of a BP-based neural net processing system for increasing the computational performance of the BPN algorithm.The training process included in the BPN algorithm requires large amount of matrix multiplication. Therefore, a SIMD-Systolic array processor has been developed to solve such a computational bottleneck. This processor is based on a VLSI array processing chip which has been designed and fabricated by using 0.6um CMOS technology. Currently, it is integrated with Pentium-100 computer through PCI local bus, and, operates at 1MHz. To multiply two matrices of sizes 8×8 and 8×256, this processing system runs 4.6 times faster than software running on Pentium-100 computer.