A Low-Cost High-Symbol-Rate Equalizer Chip for HIPERLAN System
碩士 === 國立中正大學 === 電機工程研究所 === 87 === A low-cost high-symbol-rate equalizer for the receiver of a high-speed local area network that meets the ETSI HIPERLAN standard is proposed in this thesis. Although the HIPERLAN is a Slowly Time-varying Multipath Fading Channel system, the ISI (Inter-s...
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| Format: | Others |
| Language: | en_US |
| Published: |
1999
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| Online Access: | http://ndltd.ncl.edu.tw/handle/59768310318801360628 |
| Summary: | 碩士 === 國立中正大學 === 電機工程研究所 === 87 === A low-cost high-symbol-rate equalizer for the receiver of a high-speed local area network that meets the ETSI HIPERLAN standard is proposed in this thesis. Although the HIPERLAN is a Slowly Time-varying Multipath Fading Channel system, the ISI (Inter-symbol Interference) will be very severe when the data rate up to 20Mbps. In this thesis, we select ADFE (Adaptive Decision Feedback Equalizer) to overcome the ISI problem.
We adopt the sequential architecture to reduce the ADFE hardware cost. However, a ten times operation clock frequency comparing to the parallel ADFE is applied to the whole system. Therefore the high-speed multiplier and adder are necessary for this chip. In order to solve the problem of clock skew we also embed an ADPLL (All Digital Phase-Locked Loop) to boost the operation clock frequency.
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