Low-Power Fully-Parallel Content Addressable Memory - Analysis, Design, and Application

• Main Authors: Chien-Yuan Pao, 包建元
• Other Authors: Jinn-Shyan Wang
• Format: Others
• Language: en_US
• Published: 1999
• Online Access: http://ndltd.ncl.edu.tw/handle/05060476658569781202

碩士 === 國立中正大學 === 電機工程研究所 === 87 === A partial-current-mode fully-parallel CAM is proposed in this thesis. The proposed fully-parallel CAM performs current-mode operation when either for both read data and write data, but when match data is still performed by voltage-mode. This thesis also describes several different CAM structures using different CAM cells in published paper and re-implement these CAM structures to analyze their operation and power dissipation. A 512x15-bits CAM was designed and implemented in a 0.6-mm CMOS technology, and then this design is automatically converted to a design using a 0.35-mm CMOS technology by a technology migration technique developed by the VLSI GROUP of EE/CCU. The design of the 0.35-mm version has also been submitted for fabrication. This CAM design is really used in a CCMAC control chip We have implemented a CCMAC ASIC to verify the hardware feasibility of this new architecture and also to verify the performance of the new content addressable memory. This ASIC will also be installed in a backer-upper control system.