Timing/Control Chip Design of a Wireless TDMA Personal Communications System

• Main Authors: Wen-Chieh Huang, 黃文傑
• Other Authors: Wern-Ho Sheen
• Format: Others
• Language: en_US
• Published: 1999
• Online Access: http://ndltd.ncl.edu.tw/handle/89018766937811343446

碩士 === 國立中正大學 === 電機工程研究所 === 87 === In recent years, the development of mobile communications is growing rapidly. Besides the high-tier cellular phone, the low-tier communication system with low-power, low-mobility has been widely used. The major three low-tier systems are the Japanese PHS system, the European DECT system, and the North American PACS system. The PACS is a standard adopted by ANSI for Personal Communication Systems in the United States. It is well suited to wireless local loop applications and personal communication services. It provides low-power, low-cost, high capacity, high quality, mobility, and long talk time use; also it has a rich suite of applications in urban district. In this thesis, we integrate the wireless communication system design and VLSI technologies to develop the one-chip TDMA Controller including Channel Coding, Rate Changer, and Timing/Clock/Control sub-modules. Furthermore, we make arrangements for the timing/control interface between RF module and baseband module of physical layer, and the bus interface between physical layer and data link layer. Finally, a speech-in/speech-out loop-back-testing checks the TDMA system timing and verifies the channel coding technology by observing digital signals in the logic analyzer.