Arcane: Architecture, Design and Implementation of DSP Application Core
碩士 === 中華大學 === 電機工程學系碩士班 === 87 === This thesis describes a 24-bit architecture targeting most digital signal processing (DSP) applications, such as speech, video, image, and communication. The proposed architecture is a reduced instruction set computer. It can be used as a...
Main Authors: | Jenfeng Chung, 鍾仁峰 |
---|---|
Other Authors: | Chun-Yeh Liu |
Format: | Others |
Language: | en_US |
Published: |
1999
|
Online Access: | http://ndltd.ncl.edu.tw/handle/89759722956551488284 |
Similar Items
-
Module Design of Embedded DSP Core Architecture
by: Huang Jiin-Yeh, et al.
Published: (2002) -
Embedded DSP Core Architecture for Communication Applications
by: Jin-Mao Liu, et al.
Published: (2000) -
Optimization of MPEG Audio Decoder for Embedded DSP Core
by: Shao-Jen Chung, et al.
Published: (2007) -
Design and Implementation of Dual-mode DCT IP Core and Reconfigurable DSP Processor
by: Han-Jen Hsu, et al.
Published: (2003) -
Design and Implementation of Single Issue DSP Processor Core
by: Ravinath, Vinodh
Published: (2007)