Capacity Planning for IC Test Plant

• Main Authors: Chin-Chieh Chen, 陳俊杰
• Other Authors: James C. Chen
• Format: Others
• Language: zh-TW
• Published: 1999
• Online Access: http://ndltd.ncl.edu.tw/handle/41129048640424504008

碩士 === 中原大學 === 工業工程學系 === 87 === Semiconductor manufacturing in Taiwan is growing very fast. In Final Test area, improved capacity planning is one way to increase productivity and competitiveness. In this research, a capacity planning system is proposed for a IC test plant. Four modules are developed：WIP-Pulling Module, Lot Release Module, Workload Accumulate Module, and Workload Balance Module. WIP-Pulling Module is used to caculate lot start time and finish time to meet master production schedule (MPS) using WIP information such as current operation and batch size. When WIP quantity is insufficient, Lot Release Module is called. After calculating the lot start time and finish time, Workload Accumulate Module is used to accumulate the workload of machine and jig in each day. If the workload of machine and jig are unbalanced, Workload Balance Module is used to balance these manufacturing resources. A prototype capacity planning software is developed in Microsoft Visual Basic and industrial data are used to test the performance of the capacity planning system. Based on the design of experiments, simulation results show that the capacity planning system is effective and efficient to balance the workload of manufacturing resources including machine and jig.