| Summary: | 碩士 === 逢甲大學 === 自動控制工程學系 === 87 === This thesis proposes a method which is based on the "Modified Hopfield Neural Network Based Character Recognition System" to recognize the 5 ×5 matrix characters from A to Z or the bit maps. Before designing the character recognition circuit, the structure is simulated using C language. VHDL (Very High Speed ICs Hardware Description Language) combined with the Altera software package and CPLD (Complex Programmable Logic Device) is then used to design and verify this circuit. If it is confirmed by software simulation and hardware test, we can design the character recognition circuit in the environment of Synopsys & Cadence software. Finally, chip fabrication is applied to CIC (Chip Implementation Center) after finishing the TimeMill simulation. When the circuit is designed completely, the working frequency can reach 10 MHz on simulation of Altera software package and hardware test of the CPLD. On TimeMill simulation, the working frequency can reach 20 MHz more.
In the text also mentions how to use the image processing technique together with the character recognition method proposed by this thesis to recognize characters in the documents. Initially, the image processing technique is used to convert characters in the documents into the 5 ×5 matrix characters and then the character recognition method is used to recognize the characters. For the different size characters and hand-written characters in documents, it has good effects in recognizing characters in this manner.
|
|---|
