Integrated Circuit Yield Model with Defect Source and Defect Clustering

碩士 === 國立交通大學 === 工業工程與管理系 === 87 === For the integrated circuits (IC) manufacturer, the yield of each wafer is a key index to evaluate the profit. Therefore, yield management has been developed to promote the yield quickly and effectively. One of the most important tool in the yield management is t...

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Bibliographic Details
Main Authors: Hsu-Cheng Fu, 傅旭正
Other Authors: Tong Lee-Ing
Format: Others
Language:zh-TW
Published: 1999
Online Access:http://ndltd.ncl.edu.tw/handle/99281842382907924574
Description
Summary:碩士 === 國立交通大學 === 工業工程與管理系 === 87 === For the integrated circuits (IC) manufacturer, the yield of each wafer is a key index to evaluate the profit. Therefore, yield management has been developed to promote the yield quickly and effectively. One of the most important tool in the yield management is the yield model. The conventional yield models considered only the correlation between the defect counts and the yield, consequently, the models can not predict the yield accurately. The prediction becomes worse when the wafer size increases and the defect clustering phenomenon becomes more apparent. Although the modified yield models have better prediction than that of the conventional yield model, the modified yield model are too complicated for engineers to use in practice. This study considers the effects of defect sources, defect counts and defect clustering on wafer and builds a forecasting yield model by using the neural networks. The proposed yield model not only can promote the prediction power efficiently, but also is very easy to implement. The proposed yield model is illustrated by a real case provided by an IC manufacturer in Taiwan to verify the effectiveness of the proposed yield model. Comparisons are also made among the conventional yield models, modified yield models and the proposed yield model.