Integrated Circuit Yield Model with Defect Source and Defect Clustering
碩士 === 國立交通大學 === 工業工程與管理系 === 87 === For the integrated circuits (IC) manufacturer, the yield of each wafer is a key index to evaluate the profit. Therefore, yield management has been developed to promote the yield quickly and effectively. One of the most important tool in the yield management is t...
| Main Authors: | , |
|---|---|
| Other Authors: | |
| Format: | Others |
| Language: | zh-TW |
| Published: |
1999
|
| Online Access: | http://ndltd.ncl.edu.tw/handle/99281842382907924574 |