Enhanced Dependent-Based Instruction Window for an X86 Superscalar Microprocessor

• Main Authors: Shih-Wei Perng, 彭世緯
• Other Authors: Jyh-Jiun Shann
• Format: Others
• Language: en_US
• Published: 1999
• Online Access: http://ndltd.ncl.edu.tw/handle/06548536646908150682

碩士 === 國立交通大學 === 資訊工程系 === 87 === Today, superscalar technique is widely applied to high-performance microprocessors. Because multiple instructions are decoded and more functional units are employed, the instruction window must accept more instructions from the decoder and its selection logic must select multiple instructions for execution. Therefore, the enhancement of instruction window is more and more important for designing high-performance microprocessors in the future. In this thesis, we propose two strategies to enhance the performance of dependent-based instruction window, i.e. ,FIFO Buffers. The two strategies are described as follows: 1. We replace the original selection logic of FIFO Buffers, fixed priority, by other three kinds of selection logic. The three selection logic are maximum dependence, chain length, and both (maximum dependence, chain length). The simulation results show that anyone of the three selection logic performs better than the original one. If consider the hardware cost for implementation, then the chain length is the proper selection logic. 2. We add another buffer associated with the FIFO Buffers as the instruction window. The additional buffer performs as a small centralized instruction window, and thus we called it instruction window buffer (IWB). The IWB may be very small for keeping only one to four instructions. We enforce that the IWB may keep only the ready instructions, i.e. ,all of their operands are ready. We modify the steering logic of the FIFO Buffers for adding the IWB. We use both two strategies to enhance FIFO Buffers. When the number of total entries is large, the enhanced FIFO Buffers perform better than a centralized instruction window.