Field Emission Transistor Models and IDDQ Testing for Deep Submicron VLSI

• Main Authors: Chih-Wen Lu, 盧志文
• Other Authors: Chung Len Lee
• Format: Others
• Language: en_US
• Published: 1999
• Online Access: http://ndltd.ncl.edu.tw/handle/67785175209101147592

博士 === 國立交通大學 === 電子工程系 === 87 === This dissertation contains two topics. The first topic is the field emission transistor-its model and driving circuits. The second one is the VLSI IDDQ testing-new schemes and related current sensors, either built-in or off-chip. I. Field Emission Transistor-Its Model and Driving Circuits For the modeling of field emission triode, two simple but accurate models, which can be incorporated into circuit simulation programs such as SPICE, for the field emission triode are developed. The first model is based on the Fowler-Nordheim current density-electrical field relationship but takes into account the space charge effect and the exponential-like charge distribution on the surface of the tip of the device. A procedure is developed to extract the parameters of the model. The second model is also based on the Fowler-Nordheim current density-electrical field relationship. An electric field form is adopted to calculate the current density distribution along the surface of the sphere-shape tip. The cathode current is obtained by integration of the current density over the emission surface. The gate current is derived by the same integration but over part of the emission area. A procedure to extract the values for the parameters of the model is also given. Both of the models and the procedures have been applied to experimental devices to demonstrate their accuracy. The field emission array (FEA), when used as a display device, requires a scanning driving circuit. Due to the large FEA capacitance (typically 5pF for one pixel), the driving circuit is usually slow. In this thesis, a new driving circuit, which employs the voltage controlled current source (VCCS), overcomes the above-mentioned problem, thus can reach a high driving speed. In addition, the circuit has the advantages of a uniform current driving, the gray level control and the low power consumption. II. VLSI IDDQ Testing-New Schemes and Related Current Sensors For the IDDQ testing, the distribution of defect-free IDDQ of a CMOS deep submicron VLSI circuit for the years of 2006~2012 is estimated. The estimation considers the process variation, which dominates the IDDQ variation in VLSI circuit, and different input vectors. The expected value is almost linearly proportional to the size of the circuit. However, the standard deviation is roughly proportional to the square root of the circuit size. Based on the estimation, four new IDDQ testing schemes, which compare the IDDQ currents between two input vectors or two partitioned sub-circuits (CUTs), are proposed. A fast sensing scheme, which can be applied to the Automatic Testing Equipment (ATE) and the built-in current sensor (BICS), is proposed. The transient current is rapidly bypassed by a very low resistance of a switch. The quiescent current is sampled before it reaches to a stable value. Based on the proposed IDDQ testing schemes and the sensing scheme, three types of off-chip and built-in current sensors, which are low input voltage, low power supply and high resolution, are proposed. The sensors, instead to detect the absolute value of the IDDQ currents of the CUT, compare the IDDQ currents of the CUT under different input test vectors or between the IDDQ currents of two CUTs. They have the advantages of reduction in the circuit partitioning number, low input voltage, high resolution, low power supply voltage, and improved fault detectability and diagnosability, making them very suitable to be applied to testing deep submicron digital ULSI CMOS ICs. In addition to the above three types of sensors, three types of low input voltage, low power supply, highly sensitive and fast BICSs, which can measure the absolute value of the IDDQ current, are also proposed and demonstrated.