An Improved Low Voltage/Low Power Multi-Threshold CMOS Digital Circuit Design
碩士 === 國立交通大學 === 電子工程系 === 87 === It is well known that scaling down both the supply voltage and threshold voltage is effective in reducing the power consumption while maintaining the high operation speed. However, it induces some problems, for instance, the standby power is increased dr...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | en_US |
| Published: |
1999
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| Online Access: | http://ndltd.ncl.edu.tw/handle/22350887294993081271 |