On Timing Constrained Floorplans Generation
碩士 === 國立交通大學 === 電子工程系 === 87 === In this thesis, we propose a new topology generation algorithm for floorplan designs. The algorithm is based on a graph model named edge labeling graph by labeling horizontal or vertical relationship on edges in the adjacency graph. All valid floorplan t...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | en_US |
| Published: |
1999
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| Online Access: | http://ndltd.ncl.edu.tw/handle/91919187835452500889 |