| Summary: | 碩士 === 國立交通大學 === 電子工程系 === 87 === Abstract
In this thesis, the advantage and the architecture of the pipeline ADC is described. The digital error correction technique is explained in detail. Furthermore, the error source of the pipeline analog-to-digital converter is shown and discussed. And there are some solutions to these problems in this thesis.
We also illustrate a 10bit resolution, 20MHz sampling rate pipeline ADC. The input of this architecture is a fully differential format, the input range is -1v~+1v. The component in the ADC is the residue amplifier, the comparator, the D-flipflop and the adder. The ADC has 9 stages, each stage get 2 bits and one of them is used for digital error correction. The last stage can get 2 bit. The residue amplifier is implemented by the switch capacitor circuit. The theorem of the circuit and design method is shown and discussed. The layout of the Switch-Capacitor circuit is illustrated also.
The ADC was designed using TSMC 0.6um 1P3M CMOS process by chip implement center. The simulation is done by Hspice. The spec of the ADC is 10bit resolution, 20MHz sampling rate, less than 80mW power consumption.
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