Design and Analysis of CMOS Pipeline High Speed Analog to Digital Converter
碩士 === 國立交通大學 === 電子工程系 === 87 === Abstract In this thesis, the advantage and the architecture of the pipeline ADC is described. The digital error correction technique is explained in detail. Furthermore, the error source of the pipeline analog-to-digital converter is shown...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | en_US |
| Published: |
1999
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| Online Access: | http://ndltd.ncl.edu.tw/handle/92588909541938938919 |