| Summary: | 碩士 === 國立交通大學 === 電子工程系 === 87 === With the rapidly increasing data transport rate on computer and consumer electronics, an inexpensive and high-speed method of interconnecting digital devices are needed. Most multimedia consumer electronics designers would agree that IEEE 1394 is a good candidate for interconnecting interface between digital devices in the future.
In this thesis, an IEEE 1394 PHY design is presented. It includes PHY-Link interface, arbitration controller, PHY register, timer, decoder, encoder, twisted pair ports and PLL. The analog blocks including twisted pair ports and PLL is designed using behavior model. The other parts are coded in synthesizable RTL Verilog HDL. Most functions of the IEEE 1394 including auto-configuration, transmit and receive packet, register read/write and the arbitration enhancement defined by IEEE 1394a are supported. We also analyze the IEEE 1394 bus efficiency and state some suggestions for improving bus efficiency. Finally, a verification environment for IEEE 1394 bus system is proposed. The verification environment consists of text command file, fileio engine, link layer model and PHY. The operations between two devices on the IEEE 1394 bus are verified under this verification environment. Simulation results of our PHY core are also given in this thesis.
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