| Summary: | 碩士 === 國立東華大學 === 資訊工程學系 === 87 === With the rapid advance of VLSI technology, the performance of microprocessors has improved significantly in the past years. The effect of the performance improvement stems from both the reduction of the feature size and the increased number of transistors we can put on a chip. The reduced feature size provides faster raw circuit speed. Furthermore, according to Moore's Law, the transistor count on a chip is doubled every one and half years. Hence, we can utilize more devices to enhance the VLSI architecture.
Computer architecture benefits from the rapid improvement of VLSI technology. Pipelining is a typical technique of employing more transistors to improve the performance of a microprocessor significantly. By using pipelining, the execution of different instructions can be overlapped. The potential overlap among instructions is called instruction-level parallelism (ILP). ILP can be further explored by using superscalar approach. In a superscalar microprocessor, there can be multiple functional units of the same kind, and multiple instructions can be issued concurrently. A superscalar microprocessor typically includes some hardware modules in order to dynamically schedule instructions which are ready to be issued. The modules include the reservation station and reorder buffer. Some superscalar microprocessors provide the feature of out-of-order execution, which implies out-of-order completion and requires the register renaming mechanism.
In this thesis, our focus is on the result switching network (or internal connection network), which delivers the results produced by functional units to all the reservation stations and the reorder buffer. Therefore, the result switching network is a critical element in a superscalar microprocessor. The result switching network dramatically affects the performance of a microprocessor. In our proposed design, we try to maximize the performance and also reduce the power consumption of the result switching network in a microprocessor. Our proposed design takes advantage of multiple bus scheme, which fits the superscalar architecture. With the strategy of allocating multiple bus resources for different functional units, the effective bandwidth of the result switching network is improved. Furthermore, the circuit design we propose can successfully speed up the arbitration process. In our design, the circuit signals become stable as soon as possible such that power-consuming glitches are mitigated. We have implemented our own result switching network in VLSI. The result shows that the circuit can work with 133 MHz clock rate. The gate count of the circuit is 27,000 and the maximum delay is 4.99ns.
The performance of the result switching network can be further improved through dynamically tuning the arbitration priority. The scheme of tuning arbitration priority can also reduce the power consumption for the result switching network. Finally, we describe the verification of our design and show how it works.
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