| Summary: | 博士 === 國立清華大學 === 電機工程學系 === 87 === With the ever-increasing popularity of electronic communications, data security is becoming a more and more important issue nowadays. One effective approach to secure the data transmission over an insecure channel is by the use of public-key cryptosystems.
In this dissertation, we present a practical method for bulk encryption. It combines the ElGamal and RSA public-key cryptosystems, where the former is for data encryption and the latter is for the purpose of digital signature. To implement the proposed cryptosystem, several digit-serial systolic arrays are also presented in this dissertation, including a GF(2^m) multiplier, a GF(2^m) divider, and a modular multiplier. Besides, we also present an AB^2 circuit for GF(2^m), which is more effective in computing GF(2^m) exponentiation than a GF(2^m) multiplier. All the circuits possess some attractive features in VLSI architecture design; for instance, regularity, modularity, unidirectional data flow, systolic architecture, local interconnection network, and no broadcasting signals. Moreover, they can be pipelined to bit level, so that the system clock period is independent on the selected digit size. As compared to related designs, these circuits have better performances. The proposed circuits are very useful in constructing various public-key cryptosystems, for example, Diffie-Hellman key exchange, ElGamal public-key cryptosystem, RSA public-key cryptosystem, and elliptic curve cryptosystem over GF(2^m), among others.
For the purpose of verification, a prototype chip of the proposed method for bulk encryption suitable for VDSL applications is designed and implemented. It contains a GF(2^64) multiplier, a GF(2^64) divider, and a 61-bit modular multiplier. They are used to implement a 1024-bit ElGamal cryptosystem for data encryption and a 1021-bit RSA digital signature scheme. The chip is a cell-based design, where COMPASS 0.6mm SPTM CMOS standard cell library is used. It includes 375,422 transistors and has a die size of 7384um x 7382um, where the die is packaged using a 208 CQFP. TimeMill Post Layout simulation indicates that it can be operated at a clock rate up to 111 MHz. With such a clock rate, the chip can provide a baud rate of 26.1 Mbps for data encryption and a baud rate of 13.6 kbps for digital signature.
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