The implementation of 1024 point FFT single processor

• Main Authors: Wen-Chi Chiang, 江文啟
• Other Authors: Tsin-Yuan Chang
• Format: Others
• Language: en_US
• Published: 1999
• Online Access: http://ndltd.ncl.edu.tw/handle/29695068069280338808

碩士 === 國立清華大學 === 電機工程學系 === 87 === Abstract The Discrete Fourier Transform (DFT) is considerable importance in Digital Signal Processing (DSP), instrumentation and measurement. The DFT algorithm needs enormous calculations, and therefore, the Fast Fourier Transform (FFT) exploits the symmetry and periodicity of the complex number WN to reduce the amount of calculations. High speed real-time FFT processing can be accomplished in two different ways as described below: (1) General-purpose processor approach, a single processor works at a higher clock frequency that is O (log N) times the sampling frequency, and usually costs smaller area. (2) Paralleled or pipelined processor approach: multi-processors operate on the same clock frequency close or equivalent to the sampling frequency and require larger area. In this thesis, the FFT processor would be implemented with 32-bit complex data precision based on radix-4 butterfly structure with DIF-FFT algorithm. The processor is designed for computing 1024-point FFT that is designed and simulated by Verilog hardware language and synthesis by Synopsys. The proposed processor is simulated correctly at 20MHz, and a computation of 1024-point FFT takes 64.3μs. The processor has close performance to pipelined architectures and smaller area, for being not used enormous multipliers, than pipelined architectures. The processor could be programmed more than 1024 points FFT operation with almost the only penalty of increasing memory sizes. The memory is a DRAM module without refresh circuit due to the short access time of the proposed scheme.