Design of the Control Module in a Shared Memory ATM Switch

• Main Authors: Yi-Ping Kao, 高亦平
• Other Authors: Dr.Feipei Lai
• Format: Others
• Language: zh-TW
• Published: 1999
• Online Access: http://ndltd.ncl.edu.tw/handle/43009389216737852352

碩士 === 國立臺灣大學 === 電機工程學研究所 === 87 === The demands of networks have dramatically increased in the last few years. To meet the requirements of the networks, a network must provide higher bandwidth and quality of services(QoS). And the Asynchronous Transfer Mode(ATM) network is recommended by CCITT for B-ISDN. In this thesis, we design a shared memory ATM switch that can support many ATM functions such as multicasting, OAM, and Signaling. In this switch ,it can handle sixteen input and output ports, and it's line speed is 155 Mbps. Meanwhile, to decrease packet loss ratio, we also implement three kinds of packet discarding schemes such as EPD(Early Packet Discarding), PPD(Partial Packet Discarding), and APPD(Age Priority Packet Discarding) in this switch. In the APPD Switch Controller, it has three main control modules to complete the switch operations: the I/O Controller, the Queue Manager, and the Traffic Controller. This chip is designed by me and My classmates. I am responsible for the design of the I/O Controller, and the Queue Manager. And the Traffic Controller is designed by my partner Yann.