Design and Implementation of a Baseband Processor for High Speed Wireless LAN Application

• Main Authors: Den-Kai Juang, 莊登凱
• Other Authors: Tzi-Dar Chiueh
• Format: Others
• Language: en_US
• Published: 1999
• Online Access: http://ndltd.ncl.edu.tw/handle/86311056975105473086

碩士 === 國立臺灣大學 === 電機工程學研究所 === 87 === In order to improve the performance of current wireless local area network (WLAN) , which uses direct sequence spread spectrum (DSSS) for modulation, a baseband transceiver forhigh speed WLAN application is proposed in this thesis. New modulation schemes, including M-ary bi-orthogonal keying (MBOK) and complementary code keying withlength 8 (CCK8), are proposed for high speed transmission. The system is compatible with previous DSSS modulation using the Barker sequence. An equalizer that compensates for intersymbol interference (ISI) is included in the design to better the performance under multipath fading channel. The basic principles of WLAN and its related technology are illustrated in the thesis. Functional and fixed-point simulation are performed to verify the proposed architecture. Besides the gate level netlist for ASIC design, the whole system is implemented in an FPGA emulation module. The testing results show that the proposed architecture is practical in the future. By means of further optimization on the correlator and equalizer design, the performance and cost can be further improved.