| Summary: | 碩士 === 國立臺灣科技大學 === 電子工程系 === 87 === The scaling of CMOS devices to satisfy deep submicrometer technology requirements involves several process adjustments . One of the main challenges is the formation of shallow junction . Low-energy ion implantation , in tandem with low-thermal budget annealing processes , allows us to form shallower junctions . To adopt a low thermal budget scheme , we employed long-time low-temperature furnace annealing and rapid thermal annealing（RTA）as an approach of activating the implanted dopants without significant diffusion and eliminating the implanted-induced defects .
Moreover , various low thermal budget schemes have been performed to form shallow junctions . The first scheme is the low temperature furnace annealing . The second scheme is the low temperature furnace annealing followed by RTA . The third scheme is the RTA followed by low temperature furnace annealing . The fourth scheme is the low temperature furnace annealing followed by high temperature furnace annealing . In this thesis , the dopant activation and the electrical characteristics of junctions have also been investigated .
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