Low-Power Phase-Locked Loop Design

• Main Authors: Liao Huan-Sen, 廖煥森
• Other Authors: cheng Kuo-Hsing
• Format: Others
• Language: zh-TW
• Published: 1999
• Online Access: http://ndltd.ncl.edu.tw/handle/22598479195377802704

碩士 === 淡江大學 === 電機工程學系 === 87 === Phase-locked loops are basic component used extensively in many analogy and digital systems. Such as the phase-locked loop can be used in clock recovery of communication system, and frequency synthesizer of wireless communication system. Recently, due to the mobile electronic systems developed quickly, low power consumption has become the main trade in the modern VLSI design. Thus, the goal of our paper is a low power phase-locked loop design.In the conventional digital phase-locked loop, the power consumption of the voltage-controlled oscillator has a large port, so we design voltage-controlled oscillator which has low-power consumption.The phase error of the phase-locked loop is an important parameter, but the “three-state” phase frequency detector has the dead zone, and “four-state” phase frequency detector makes the charge pump have phase offset because it has large gain when the phase-locked loop near locked. Thus we proposed a “three-state” and only few dead zone phase frequency detector to reduce the phase error of the phase-locked loop.Finally, we will complete chip of the low-power phase-locked loop, and prove the feasibility of our design.