Study on Instruction Reuse in RISC Architecture

• Main Authors: Yichen Liu, 劉亦峻
• Other Authors: Jong-Jiann Shieh
• Format: Others
• Language: en_US
• Published: 1999
• Online Access: http://ndltd.ncl.edu.tw/handle/18040065311862631235

碩士 === 大同工學院 === 資訊工程研究所 === 87 === Trace is a dynamic instruction sequence. Trace cache captures dynamic instruction sequences that are built up as program executes. If a predicted dynamic sequence exists in the trace cache, it can be fed directly to the execution engine. The length of a trace is limited in two ways - by number of instructions "n" and by number of blocks "m". The block breaks off by branch instruction. In trace cache, every cache line contains additional state information to identify the trace. A trace hit requires comparing the trace-id with fetching address and branch prediction result. On a trace cache hit, an entire trace of instructions is fed into the instruction latch, bypassing the instruction cache. If a trace that is nonexistent in trace cache, the execution engine fetches a block of instructions (terminated by branch instruction) from instruction cache. The basic blocks are latched in instruction latch and line-fill buffer; the magic logic serves to merge each incoming block of instructions with preceding instructions in the line-fill buffer. Filling is complete when either "n" instructions have been traced or "m" branches have been detected in the trace. At this point the contents of the line fill buffer are written into the trace cache. The additional state information per trace is generated during the line-fill process. In this thesis, we will implement trace cache with verilog HDL and simulate it in behavior level. Final, we will combine the trace cache with upgrade data speculative technology that we purpose to support highly parallel execution engines. The mixed instruction and data reuse mechanism will overcome both instruction-flow and data-flow limitations whichever becomes performance bottleneck in current micro-processors. Thus, the aggressive reuse mechanism will be an important component of future microprocessors and improve performance monumentally.