The Design and Implementation of a 512~2048 bit Scalable RSA Encryption/Decryption System

• Main Authors: Chang-Cheng Lin, 林丈棖
• Other Authors: Sau-Mou Wu
• Format: Others
• Language: zh-TW
• Published: 1999
• Online Access: http://ndltd.ncl.edu.tw/handle/60502011058267231901

碩士 === 元智大學 === 電機與資訊工程研究所 === 87 === In this thesis we design a 512-bit to 2048-bit scalable RSA public key encryption/decryption system. The H algorithm is used to translate the modular exponentiation in a RSA cryptosystem into a sequence of Montgomery’s operations. And we can combine several 16-bit Montgomery’s modules into a complete Montgomery’s unit which can achieve n-bit Montgomery’s operation, where n can be any bit number of keys. The Montgomery’s Unit is designed in a fully pipelined architecture. Its complexity of time is O(n). And the Control Unit is designed in 256-bit, 512-bit, 1024-bit, and 2048-bit modes. It’s a complete RSA cryptosystem when the Control Unit is combined with a modularized Montgomery’s Unit with suitable bit length. The system clock is set to 25MHz. From the simulation result of Altera CPLD 6K series, it takes about 3*n2 clocks to finish an operation of a n-bit RSA encryption or decryption. For example, each encryption or decryption will take about 3*5122 clocks to calculate in a 512-bit RSA cryptosystem.