PLPP Design for ITU-T G.832 E3 Signal
碩士 === 國立中正大學 === 電機工程研究所 === 88 === Abstract Asynchronous Transfer Modes (ATM) over Asymmetric Digital Subscriber Line (ADSL) provides a high-speed access to the Internet. User data can be concentrated in a high-speed interface (STM-1, DS3 or E3) connected to an ATM switch by a Digital...
| Main Authors: | , |
|---|---|
| Other Authors: | |
| Format: | Others |
| Language: | zh-TW |
| Published: |
2000
|
| Online Access: | http://ndltd.ncl.edu.tw/handle/30647036358511062189 |
| Summary: | 碩士 === 國立中正大學 === 電機工程研究所 === 88 === Abstract
Asynchronous Transfer Modes (ATM) over Asymmetric Digital Subscriber Line (ADSL) provides a high-speed access to the Internet. User data can be concentrated in a high-speed interface (STM-1, DS3 or E3) connected to an ATM switch by a Digital Subscriber Line Access Multiplexer (DSLAM). The design of a Physical Layer Protocol Processor (PLPP) in the high-speed interface is required if signal transport in the conventional telecommunication network is needed. In this paper, the PLPP for ITU-T G.832 E3 signal is designed by an FPGA(Field Programmable Gate Array). A high-speed board integrates the E3 PLPP with the cell multiplexer function for evaluating E1 signals segmented/re-assembled by the ATM AAL1 processor. Long term test was performed to verify the performance of the E3 PLPP.
|
|---|