| Summary: | 碩士 === 國立中正大學 === 電機工程研究所 === 88 === This paper describes an automatic microcontroller design system, which can produce the most simplified microcontroller-architecture according to application program, and reduce the designing time caused by artificial oversight at the same time. Moreover, automatic microcontroller design system can cut down the cost of research and design.
In the beginning, the microcontroller-architecture based on ADL (Architecture Description Language) and CBDL (Component Behavior Description Language) are described. Then, the ADL and CBDL will be translated RTL Verilog code based on a translator, which is developed in this thesis. The RTL Verilog code of an 8-bit RISC microcontroller will be verified and implemented by a FPGA and ASIC.
Due to the incompletion of definition of ADL and CBDL, moduling microcontroller design system based on Verilog will be proposed. This method can reduce the developed the difficult of translator. The moduling microcontroller design system produces the most simplified microcontroller-architecture implemented by RTL Verilog which can be adapted the application specific program. Then, it can be easy to proceed to the design flow of ASIC Cell-Based.
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