| Summary: | 碩士 === 義守大學 === 電子工程學系 === 88 === This thesis is to study the method of reducing the operational amplifier input offset voltage by using a self-calibration technique. The circuits consist of the initialization unit, control unit, oscillator, successive approximation registers and DAC unit. At the power-up stage, the detected input offset voltage is converted to digital data, which are saved in registers. The multipath operational amplifier, after being calibrated, has extremely low input offset voltage. We apply this self-calibration structure to the operational amplifier we developed before. This will add high DC accuracy to the advantage of high gain and wide bandwidth already existing in our operational amplifier. Such structure is mixed-signal in nature[1]. We use the CADANCE tools to design our circuits.
Reduction of crosstalk between digital and analog parts is a challenge to confront with[2]. Also, to promote the system performance, minimization of chip area and maximization of conversion speed are also subjects of this thesis.
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