ASIC implementationof DCT
碩士 === 義守大學 === 電子工程學系 === 88 === With the significant property of high signal density, discrete cosine transform (DCT) has been applied in many fields of digital signal processing. The design of the DCT or IDCT chips need to consider several important factors such as the chip area, runni...
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| Format: | Others |
| Language: | zh-TW |
| Published: |
2000
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| Online Access: | http://ndltd.ncl.edu.tw/handle/95414103571037761257 |
| Summary: | 碩士 === 義守大學 === 電子工程學系 === 88 === With the significant property of high signal density, discrete cosine transform (DCT) has been applied in many fields of digital signal processing. The design of the DCT or IDCT chips need to consider several important factors such as the chip area, running frequency and delay time. In this paper, we develop an architectures for DCT computation and compared with architectures that other authors presented before. The ASIC implementation for these DCT architectures is carry out by using Verilog hardware description language to synthesis the cell-based and an Altera Flex 10 k chip.
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