A PLL Frequency Synthesizer Based on DSP-Architecture for Frequency-Hopping Wireless Communication Systems

• Main Authors: Yung-Hsun Liu, 劉勇勳
• Other Authors: Huey-Ru Chuang
• Format: Others
• Language: zh-TW
• Published: 2000
• Online Access: http://ndltd.ncl.edu.tw/handle/10049572737690861523

碩士 === 國立成功大學 === 電機工程學系 === 88 === A 2.4GHz PLL frequency synthesizer, based on DSP-architecture for frequency-hopping wireless communication systems, are designed, implemented, and tested. The frequency synthesizer, different from the traditional architecture, uses the DSP-chip TMS320C50 as the synthesizer loop controller for fast loop locking. For frequency hopping function, the values of dividing ratio associated with each PN code are computed and stored in DSP memory. One of the configurations of this frequency synthesizer has 31/63channels, with a channel-bandwidth 1.06/0.53MHz. The measured phase noise and the output power of the realized frequency synthesizer are about —83 dBc/Hz (@10kHz) and 4dBm. The switching time between two adjacent channels and the first to last channels are about 250us and 440 us. The realized frequency synthesizer is incorporated with a 2.4GHz transmitter and receiver RF front-end modules (without tracking/synchronization circuits) to test frequency hopping function. The measurements include different configurations, such as fixed LO frequency, frequency hopping with or without in-band interference signal, and various hopping channel numbers and speeds. The measured results show that the realized frequency synthesizer for frequency hopping operation has a good performance to suppress the interference signal. This is very important for wireless communication applications.