| Summary: | 碩士 === 國立成功大學 === 電機工程學系 === 88 === This paper adopts two different algorithms:Blakley algorithm and Montgomery algorithm, and proposes three hardware designs totally. To speed up chip’s performance in Blakley based hardware, we prefer carry save adder rather than carry propagate adder. In Montgomery based chip design, we propose two different hardware structures.
In our design, N is 1024 bits long. And we use Xilinx FPGA 4044-3 to verify the RSA hardware chip design. The Chip can be controlled by external 8-bit processor. It has 15 pins, including power pins VCC,GND,clock,reset,birectional 8-bit data pins,and other 3 pins as asynchronous transmission. According to our research on Blakley based chip design, if this chip works at 50M Hz, the total time is about 0.1 sec.
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