A Digital Frequency Synthesizer HDL Generator for SOC Design

• Main Authors: Chung-Cheng Wang, 王中正
• Other Authors: Chen-Yi Lee
• Format: Others
• Language: en_US
• Published: 2000
• Online Access: http://ndltd.ncl.edu.tw/handle/21752521694156829949

碩士 === 國立交通大學 === 電子工程系 === 88 === With the rapid advance in CMOS technology, the trend of the VLSI design is then towards system-on-chip (SOC) where design methodology, cost, and turnaround time are major issues. Concepts of intellectual property (IP) are then proposed to fit for SOC designs. Based on a digital frequency synthesizer (DFS) controller IP, a 900 MHz frequency synthesizer is proposed to fit in with the wireless LAN (local area network) applications, which provides low cost and efficient design periods. A full-custom voltage-controlled oscillator (VCO) is designed to achieve the system requirements and generate such a high-speed frequency. Its output frequency range can be from 865 MHz to 1038 MHz. In order to solve the interface between the DFS controller IP and the VCO and provide a digital-to-voltage conversion, a novel cell-based digital-to-voltage converter (DVC) is proposed, too. This DVC only uses inverters and tri-state inverters, which are common and various elements in a cell library. The cell-based manner gives a low-cost and portable design methodology of the digital-to-voltage conversion. Characteristic equations of the DVC are also derived. Output voltages can be then obtained from those equations with good accuracy and efficiency. The 900 MHz frequency synthesizer is fabricated in TSMC 0.6 mm single-poly-triple-metal (SPTM) CMOS technology. The measurement results show that the divided-by-ten output frequency has a peak-to-peak jitter of 82 ps with root-mean-square (RMS) value of 11.89 ps. The DVC resolution can achieve 0.5 mV. At last, a program named CCDFS is developed to automatically generate the DFS controller IP according to system specifications. All issues about the DFS controller IP during cell library transfers and process migrations are considered in this program. This makes the DFS controller IP more flexible and practical. It also reduces design turn-around time and increases efficiency in the SOC design indeed. Web version of CCDFS is also online now, which provides a user-friendly interface and allows users to access via the powerful Internet.