| Summary: | 碩士 === 國立交通大學 === 電機與控制工程系 === 88 === This thesis proposes the design and implementation of a 3-level inverter for motor drive application. The implementation method uses natural-point-clamp topology for the topology of 3-level inverter and uses space vector pulse width modulation (SVPWM) for the voltage command. The kernel of whole control loop is based on DSP (TMS320F240) developed by TI which output voltage command signal drive power stage. In this thesis, first, various topologies have been reported in detail for high power drive application in the recent literature. Second, the topology used in this thesis is the natural-point-clamp topology that has been commodity abroad recently. The advantages of 3-level inverter are low harmonic and low cost then conventional 2-level inverter. Final, under low power condition, we construct a 3-level inverter experiment system. From the experiment results, it can be easily extend to high power applications in industry.
|
|---|
