VLSI Implementation of A Coefficient Adjustable Architecture for 1-D Discrete Wavelet Transform

• Main Authors: Yuan-Chang Chen, 陳元章
• Other Authors: Ching-Huang Wei
• Format: Others
• Language: en_US
• Published: 2000
• Online Access: http://ndltd.ncl.edu.tw/handle/00532668813904640169

碩士 === 國立高雄第一科技大學 === 電腦與通訊工程系 === 88 === In recent years, discrete wavelet transform (DWT) is generally used in various signal applications, for example, signal processing, image compression, computer vision, and image recognition. Even it is used of the new JPEG-2000 and MPEG-4 standards for image and video compressions. However, it always needs a large amount of computation time to perform discrete wavelet transform. For high-speed and lower-cost applications in image and audio, discrete wavelet transform hardware is needed and several VLSI architectures are very noticeable and instant. The basic schematic for achieving the discrete wavelet transform is a pyramid structure which is constructed by multiple stages of filter banks and subsample schemes. Each stage of filter bank consists of a low-pass and a high-pass filters and each filter is cascaded by a subsample scheme. The low-pass filter of each stage has the same impulse response, and the high-pass filter of each stage also has the same impulse response. In this paper we present an efficient fold-systolic VLSI architecture for computing the discrete wavelet transform. In addition, any user can input the coefficient values of filter bank or can use the default filter coefficients of Daubechies 6-tap wavelets. The basic operation of convolution is multiplication and accumulation. Thus, we use a faster speed multiplier to instead of the Booth multiplier. The new architecture of multiplexer-based array multiplier is proposed by Dr. Pekmestzi in 1999. The discrete wavelet transform architecture contains two stages of filter banks to achieve a high throughput and an optimal computation time. The features of this architecture are shorter latency, easy to control, regular structure for VLSI implementation and lower hardware cost. This architecture is designed and simulated by using VHDL as well as it is verified by SYNOPSYS and CADENCE tools. Finally, this chip is fabricated in a 0.35m CMOS technology supported by Chip Implementation Center (CIC) in R.O.C..