Automatic Optimization in Pass-Transistor-Based Logic Synthesizer

• Main Authors: Chih-Cheng Hsu, 許志成
• Other Authors: Shen-Fu Hsiao
• Format: Others
• Language: zh-TW
• Published: 2000
• Online Access: http://ndltd.ncl.edu.tw/handle/86877104888035726165

碩士 === 國立中山大學 === 資訊工程學系研究所 === 88 === In this thesis, An automatic optimization logic synthesizer in pass-transistor-based is developed for logic mapping of the combinational circuits. The format of inputs is Boolean functions with expression of sum of product and we can input several functions for hardware sharing at the same time. Depending the difference of circuits, we use the RC delay model to do optimization for both area and speed performance. The final, output is Verilog gate-level code and HSPICE netlist that provide Verilog-in for automatic place-and-route and simulation. It only needs little executing time for searching the best result and we can quickly gate it.